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281
ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
Cisco
Pune, India
India
O1mo
282
ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)
Cisco
Pune, India
India
1mo
283
Senior Software Engineer, Wireless Radio / Firmware - 7+ yrs | BLR
Cisco
Bangalore, India
India
1mo
284
Senior Software Development Engineer in Test (SDET), Hybrid, RTP, NC
Cisco
RTP, North Carolina, US
United States
H1mo
285
Software Engineering Technical Leader
Cisco
Bangalore, India
India
1mo
286
ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)
Cisco
Pune, India
India
O1mo
287
Senior Engineering Manager, AI
Cisco
Seattle, Washington, US / Austin, Texas, US / RTP, North Carolina, US / Houston, Texas, US / Nashville, Tennessee, US / Washington, District of Columbia, US / San Diego, California, US / Bellevue, Washington, US
United States
2mo
288
ASIC DFT Engineering Technical Leader | Scan, ATPG, MBIST
Cisco
Bangalore, India / Hyderabad, India
India
2mo
289
ASIC Engineering Technical Leader- STA
Cisco
San Jose, California, US
United States
2mo
290
Network Systems Engineer - Data Center AI Network Engineer
Cisco
Bangalore, India / Hyderabad, India
India
2mo
291
Leader, Software Engineering
Cisco
Tel Aviv-Yafo, Israel
Israel
O2mo
292
Software Engineer, Information Experience
Cisco
RTP, North Carolina, US
United States
2mo
293
Software Engineer
Cisco
London, United Kingdom
United Kingdom
H2mo
294
ASIC Design Verification Engineer | UVM | Exp 8+ Years
Cisco
Bangalore, India
India
2mo
295
Technical Leader, Software Engineer (AI Canvas)
Cisco
Milpitas, California, US
United States
2mo
296
ASIC Engineering Analog Design Leader:ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 10+ years
Cisco
Bangalore, India
India
2mo
297
ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years
Cisco
Bangalore, India
India
2mo
298
Kubernetes Platform Engineer - AI Infrastructure ( Golang/Python) - (8+ Years)
Cisco
Bangalore, India
India
2mo
299
ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ years
Cisco
Bangalore, India
India
2mo
300
Kubernetes Platform Engineer - AI Infrastructure (8+ Years)
Cisco
Bangalore, India
India
2mo
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